This invention relates generally to integrated circuits and in particular to static pass transistor logic with transistors with multiple vertical gates.
Many logic circuits include multiple transistors arrayed such that a combination of activated transistors produce a logical function. Such transistors in the array are activated, in the case of MOSFET devices, by either applying or not applying a potential to the gate of the MOSFET. This action either turns on the transistor or turns off the transistor. Conventionally, each logical input to the logic circuit is applied to an independent MOSFET gate. Thus, according to the prior art, a full MOSFET is required for each input to the logic circuit. Requiring a full MOSFET for each logic input consumes a significant amount of chip surface area. Conventionally, the size of each full MOSFET, e.g. the space it occupies, is determined by the minimum lithographic feature dimension. Thus, the number of logical functions that can be performed by a given logic circuit is dependent upon the number of logical inputs which is dependent upon the available space to in which to fabricate an independent MOSFET for each logic input. In other words, the minimum lithographic feature size and available surface determine the functionality limits of the logic circuit.
Pass transistor logic is one of the oldest logic techniques and has been described and used in NMOS technology long before the advent of the CMOS technology currently employed in integrated circuits. A representative article by L. A. Glasser and D. W. Dobberpuhl, entitled xe2x80x9cThe design and analysis of VLSI circuits,xe2x80x9d Addison-Wesley, Reading Mass., 1985, pp. 16-20, describes the same. Pass transistor logic was later described for use in complementary pass transistor circuits in CMOS technology. Articles which outline such use include articles by J. M. Rabaey, entitled xe2x80x9cDigital Integrated Circuits; A design perspective,xe2x80x9d Prentice Hall, Upper Saddle River, N.J., pp. 210-222, 1996, and an article by K. Bernstein et al., entitled xe2x80x9cHigh-speed design styles leverage IBM technology prowess,xe2x80x9d MicroNews, vol. 4, no. 3, 1998. What more, there have been a number of recent applications of complementary pass transistor logic in microprocessors. Articles which describe such applications include articles by T. Fuse et al., entitled xe2x80x9cA 0.5V 200 mhz 1-stage 32b ALU using body bias controlled SOI pass-gate logic,xe2x80x9d Dig. IEEE Int. Solid-State Circuits Conf., San Francisco, pp. 286-287, 1997, an article by K. Yano et al., entitled xe2x80x9cTop-down pass-transistor logic design,xe2x80x9d IEEE J. Solid-State Circuits, Vol. 31, no. 6, pp. 792-803, June 1996, and an article by K. H. Cheng et al., entitled xe2x80x9cA 1.2V CMOS multiplier using low-power current-sensing complementary pass-transistor logicxe2x80x9d, Proc. Third Int. Conf. On Electronics, Circuits and Systems, Rodos, Greece, 13-16 October, vol. 2, pp. 1037-40, 1996.
In another approach, differential pass transistor logic has been developed to overcome concerns about low noise margins in pass transistor logic. This has been described in an article by S. I. Kayed et al., entitled xe2x80x9cCMOS differential pass-transistor logic (CMOS DPTL) predischarge buffer design,xe2x80x9d 13th National Radio Science Conf., Cairo, Egypt, pp. 527-34, 1996, as well as in an article by V. G. Oklobdzija, entitled xe2x80x9cDifferential and pass-transistor CMOS logic for high performance systems,xe2x80x9d Microelectronic J., vol. 29, no. 10, pp. 679-688, 1998. Combinations of pass-transistor and CMOS logic have also been described. S. Yamashita et al., xe2x80x9cPass-transistor? CMOS collaborated logic: the best of both worlds,xe2x80x9d Dig. Symp. On VLSI Circuits, Kyoto, Japan, 12-14 June, pp. 31-32, 1997. Also, a number of comparisons of pass transistor logic and standard CMOS logic have been made for a variety of different applications and power supply voltages. These studies are described in an article by R. Zimmerman et al., entitled xe2x80x9cLow-power logic styles: CMOS versus pass transistor logic,xe2x80x9d IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079-1790, July 1997, and in an article by C. Tretz et al., xe2x80x9cPerformance comparison of differential static CMOS circuit topologies in SOI technology,xe2x80x9d Proc. IEEE Int. SOI Conference, October 5-8, FL, pp. 123-4, 1998.
However, all of these studies and articles on pass transistor logic have not provided a solution to the constraints placed on logic circuits by the limits of the minimum lithographic feature size and the deficit in the available chip surface space.
An approach which touches upon overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space, is disclosed in the following co-pending, commonly assigned U.S. patent applications by Len Forbes and Kie Y. Ahn, entitled: xe2x80x9cProgrammable Logic Arrays with Transistors with Vertical Gates,xe2x80x9d Ser. No. 09/583,584, now issued as U.S. Pat. No. 6,420,902, xe2x80x9cHorizontal Memory Devices with Vertical Gates,xe2x80x9d Ser. No. 09/584,566, and xe2x80x9cProgrammable Memory Decode Circuits with Vertical Gates,xe2x80x9d Ser. No. 09/584,564, now issued as U.S. Pat. No. 6,219,299. Those disclosures are all directed toward a non volatile memory cell structure having vertical floating gates and vertical control gates above a horizontal enhancement mode channel region. In those disclosures one or more of the vertical floating gates is charged by the application of potentials to an adjacent vertical gate. The devices of those disclosures can be used as flash memory, EAPROM, EEPROM devices, programmable memory address and decode circuits, and/or programmable logic arrays. Those applications, however, are not framed to address overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space for purposes of pass transistor logic.
Therefore, there is a need in the art to provide improved transistor logic technology which overcomes these barriers.
The above mentioned problems with pass transistor logic and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided for static pass transistor logic having transistors with multiple vertical gates. The multiple vertical gates are edge defined such that only a single transistor is required for multiple logic inputs. Thus a minimal surface area is required for each logic input.
In one embodiment of the present invention, a novel static pass transistor is provided. The novel static pass transistor has a horizontal depletion mode channel region between a single source and drain region. A number of vertical gates are located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. At least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material.
The techniques described here produce logic gates where each logic input is less that one transistor. In a conventional NMOS NAND logic circuit each logic input goes to the gate of a separate transistor each with a source, drain and gate, here there is no source nor drain region associated with each input and the gates have sub-lithographic horizontal dimensions by virtue of being edge defined vertical gates. This results in a minimal area being associated with each logic input.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
FIG. 1A illustrates a novel static pass transistor according to the teachings of the present invention.
FIG. 1B is a schematic illustration of the novel static pass transistor shown in FIG. 1A.
FIG. 1C is an illustration of the operation of the novel static pass transistor described in connection with FIGS. 1A and 1B.
FIG. 1D is another characterization of the novel static pass transistor of FIG. 1C.
FIG. 1E is a further illustration showing that depletion mode n-channel MOSFETs are xe2x80x9conxe2x80x9d with zero gate voltage and that a negative applied gate voltage turns xe2x80x9coffxe2x80x9d the depletion mode n-channel.
FIG. 2A illustrates one embodiment for the variance between the first oxide thickness (t1) and the second oxide thickness (t2) in the novel static pass transistor of the present invention.
FIG. 2B is an energy band diagram illustrating the effect on the conduction in the depletion mode channel beneath the first oxide thickness (t1) when a zero Volts gate potential (Vg) is applied above according to one embodiment of the present invention.
FIG. 2C is an energy band diagram illustrating the effect on the conduction in the depletion mode channel beneath the first oxide thickness (t1) with a negative applied gate potential (Vg) of approximately xe2x88x920.6 Volts.
FIG. 3A is an illustration of another embodiment configuration for the novel static pass transistor of the present invention.
FIG. 3B is another characterization of the novel static pass transistor of FIG. 3A.
FIG. 4A is an illustration of another operational state for the novel static pass transistor shown in FIGS. 3A and 3B.
FIG. 4B is another characterization of the novel static pass transistor of FIG. 4A.
FIG. 5 illustrates an embodiment of the novel static pass transistors of the present invention in a pass transistor logic (PTL) circuit.
FIG. 6 illustrates a complementary pass transistor logic (CPTL) circuit embodiment employing the novel static pass transistors of the present invention.
FIG. 7 illustrates a complementary pass transistor logic (CPTL) circuit embodiment for an adder circuit 701 employing the novel static pass transistors of the present invention.
FIGS. 8A-8F illustrate one method for forming the novel static pass transistors of the present invention.
FIGS. 9A-9D illustrate an embodiment of a variation on the fabrication process shown in FIGS. 8A-8F.
FIGS. 10A-10C illustrate another embodiment of a variation on the fabrication process to make all of the gates over thin gate oxides.
FIGS. 11A-11D illustrate another embodiment of a variation on the fabrication process to allow the fabrication of different gate oxide thicknesses under various gates to make some lines active and others as passing lines.
FIGS. 12A and 12B are illustrations of an embodiment in which a number of input lines which collectively pass over multiple MOSFET logic cells is a logic circuit block, can be contacted at the edge of a logic circuit according to the teachings of the present invention.
FIG. 13 illustrates a block diagram of an embodiment of an electronic system according to the teachings of the present invention.